Ananda Samajdar

Synergy Lab @ Georgia Tech

I am a PhD student at the department of Electrical and Computer Engineering (ECE) at Georgia Tech. I am working with Prof. Tushar Krishna as a part of the Synergy group. I completed Bachelors of Technology (Hons.) in Electronics and Communication Engineering(ECE) from Indian Institute of Information Technology, Allahabad in 2013.

The focus of my research has been on custom architecture design with emphasis on machine learning acceleration. Over the past few years I've led and participated in project aimed to find efficient architectures for Deep Neural Network inference and training. A major focus of my work has also been to develop architectures which enable independent deployment of machine learing algorithms on the edge.

Research

We have recently published a book titled "Data Orchestration in Deep Learning Accelerators".
Proper data orchestaration is one of the main factors to extract perfromance and energy efficincy in deep neural network accelerators. In this book we describe the various techniques that have emerged over the years to optimize data movement to optimize accelerator design goals.
Our intention through this book is to familarize the reader via case studies of exisiting design and example accelerators, to help get up to speed realtively quickly. We hope this book serves as a useful tool for researches new to this field as well as for veterans in the need for a reliable reference.


Here are a few recent projects I've worked on.

SCALE-Sim

SCALE-Sim : Systolic CNN AcceLErator Simulator

MAERI

Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects

Publications

  1. A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim
    Ananda Samajdar, Jan Moritz Joseph, Yuhao Zhu, Paul Whatmough, Matthew Mattina, and Tushar Krishna
    IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2020)

  2. CLAN: Exploring Continuous Learning on Commodity Edge Devices using Asynchronous Distributed Neuroevolution
    Parth Mannan, Ananda Samajdar, and Tushar Krishna
    IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2020)

  3. SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training
    Eric Qin, Ananda Samajdar, Hyoukjun Kwon, Vineet Nadella, Sudarshan Srinivasan, Dipankar Das, Bharat Kaul, and Tushar Krishna
    International Symposium on High Performance Computer Architecture (HPCA-2020)
    [Best paper award]

  4. Scaling the Cascades: Interconnect-aware FPGA implementation of Machine Learning problems
    Ananda Samajdar, Tushar Garg, Tushar Krishna, and Nachiket Kapre
    29th International Conference on Field Programmable Logic and Applications (FPL-2019)

  5. GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware
    Ananda Samajdar, Parth Mannan, Kartikay Garg and Tushar Krishna
    ACM/IEEE 51th International Symposium on Microarchitecture (MICRO-2018)

  6. Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision
    Yuhao Zhu, Ananda Samajdar, Matthew Mattina and Paul Whatmough
    ACM/IEEE 45th International Symposium on Computer Architecture (ISCA-2018)
    [Honorable Mention, IEEE MICRO Top Pick 2018]

  7. MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects
    Hyoukjun Kwon, Ananda Samajdar, and Tushar Krishna
    23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-2018) [Honorable Mention, IEEE MICRO Top Pick 2018]

  8. Rethinking NoCs for Spatial Neural Network Accelerators
    Hyoukjun Kwon, Ananda Samajdar, and Tushar Krishna
    ACM International Symposium on Network-on-Chip (NOCS-2017)
Non archived
  1. SCALE-Sim: Systolic CNN Accelerator Simulator
    Ananda Samajdar, Yuhao Zhu, Paul Whatmough, Matthew Mattina, and Tushar Krishna
    arXiv preprint arXiv:1811.02883

  2. Enabling Continuous Learning through Neural Network Evolution in Hardware
    Ananda Samajdar, Kartikay Garg and Tushar Krishna
    3rd workshop on Cognitive Architectures (CogArch-2018)

  3. Algorithm-SoC Co-Design for Energy-Efficient Mobile Continuous Vision
    Yuhao Zhu, Ananda Samajdar, Matthew Mattina and Paul Whatmough
    3rd workshop on Cognitive Architectures (CogArch-2018)

  4. MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Programmable Interconnects
    Hyoukjun Kwon, Ananda Samajdar, and Tushar Krishna
    SysML Conference (Sysml-2018)
Please refer to my google scholar profile for the complete list.

Work Experience

I interned at ARM Research from May-Nov 2017, with the machine learning research group. I spent my time there working on accelerator and interface design for machine learning worklaods.

Prior to joining Gatech I was working full time as front end VLSI design engineer at Qualcomm Bangalore from 2013 to 2016. My work involved SoC level RTL integration, power management subsystem design and SoC power ananlysis.

I interned at CHiPES lab at NTU Singapore as a research assistant with Prof T Srikanthan during my final semester. I also worked with the HW Apps team at Qualcomm BDC as an intern in 2012.

For more information see my LinkedIn profile.

Contact Me

You can reach out to me via email:
anandsamajdar [at] gatech [dot] edu

If you are in campus, drop by to say hi!
3305, Klaus Advanced Computing Building
266, Ferst Dr NW, Atlanta, GA, 30332